Key Responsibilities
- Develop and maintain ASIC verification environments using SystemVerilog and UVM
- Write test plans and test cases to validate ASIC designs against specifications
- Debug and analyze simulation failures to identify root causes
- Collaborate with design teams to ensure comprehensive coverage and sign-off
- Automate verification processes to improve efficiency and reduce time-to-market
- Participate in code reviews and contribute to verification methodology improvements
Requirements
- Bachelor's or Master's degree in Electrical Engineering or related field
- 3+ years of experience in ASIC verification with SystemVerilog/UVM
- Strong understanding of ASIC design flows and verification methodologies
- Proficiency in scripting languages like Perl or Python
- Experience with formal verification tools is a plus