Key Responsibilities
- Implement Design for Test (DFT) methodologies in chip designs
- Develop and optimize scan insertion, ATPG, and BIST flows
- Collaborate with RTL designers to ensure testability of complex SoCs
- Generate and validate test patterns for manufacturing test
- Troubleshoot DFT-related issues in silicon bring-up
- Automate DFT processes using Python and EDA tools
Requirements
- 5+ years of experience in DFT for semiconductor designs
- Expertise in scan insertion, ATPG, and JTAG boundary scan
- Proficiency in Verilog and scripting languages (Python, Tcl)
- Experience with EDA tools (Synopsys, Cadence, Siemens EDA)
- Strong understanding of semiconductor test methodologies