Key Responsibilities
- Perform physical verification of ASIC designs using industry-standard tools
- Run DRC (Design Rule Check) and LVS (Layout vs. Schematic) checks
- Debug and resolve physical verification issues in layouts
- Collaborate with design and implementation teams to ensure manufacturability
- Automate verification processes using TCL scripting
- Ensure compliance with foundry-specific design rules
Requirements
- Bachelor's or Master's in Electrical Engineering or related field
- 3+ years of experience in physical verification
- Proficiency in IC Compiler, Calibre, or similar tools
- Strong understanding of DRC and LVS concepts
- Experience with TCL scripting for automation