We are seeking a highly motivated and detail-oriented RTL & Co-design Engineer (junior) to join our team. As a junior engineer, you will be responsible for designing and developing RTL and co-design solutions for AI-related projects. You will work closely with our team of experienced engineers to develop and implement cutting-edge technologies.
Key Responsibilities:
- Design and develop RTL and co-design solutions for AI-related projects.
- Collaborate with cross-functional teams to develop and implement new technologies.
- Develop and maintain high-quality code in Verilog and SystemVerilog.
- Participate in code reviews and contribute to the improvement of our design and development processes.
- Stay up-to-date with the latest advancements in RTL and co-design technologies.
Requirements:
- 2+ years of experience in RTL design and co-design.
- Strong understanding of Verilog and SystemVerilog.
- Experience with Python programming language.
- Excellent problem-solving skills and attention to detail.
- Ability to work in a fast-paced environment and meet deadlines.