About the Role
NVIDIA is looking for a Senior Staff ASIC Design Engineer to join our dynamic and fast-paced team. In this role, you will be a key contributor to the design and development of cutting-edge GPUs and other high-performance ASICs. You will be responsible for various aspects of the ASIC design flow, from micro-architecture definition to silicon bring-up, focusing on delivering high-quality, high-performance, and power-efficient designs.
Responsibilities
- Lead and contribute to the micro-architecture definition and RTL design of complex digital blocks and sub-systems.
- Perform logic design, synthesis, static timing analysis (STA), and formal verification.
- Collaborate with verification teams to ensure robust functional verification and achieve coverage goals.
- Work closely with physical design teams on floor planning, place & route, and physical verification to achieve timing closure and meet power targets.
- Develop and implement design for testability (DFT) structures and methodologies.
- Participate in silicon bring-up and debugging activities.
- Drive design methodology improvements and propose innovative solutions to complex design challenges.
- Mentor junior engineers and contribute to a collaborative team environment.
Requirements
- BS/MS in Electrical Engineering or Computer Engineering with 8+ years of experience in ASIC design.
- Strong expertise in digital design principles, RTL design using Verilog/SystemVerilog, and synthesis.
- In-depth understanding of clocking, reset, and clock domain crossing (CDC) techniques.
- Solid experience with static timing analysis (STA), power analysis, and low-power design techniques.
- Proficiency in using industry-standard EDA tools for design, simulation, and verification.
- Experience with scripting languages such as Perl or Python for design automation.
- Knowledge of physical design concepts, including floorplanning, place and route, and physical verification.
- Familiarity with DFT concepts and methodologies.
- Excellent problem-solving, analytical, and debugging skills.
- Strong communication and interpersonal skills, with the ability to work effectively in a team environment.
Desired Skills
- Experience with UVM/SystemVerilog verification methodologies.
- Familiarity with various memory interfaces (DDR, HBM) and high-speed protocols (PCIe, MIPI).
- Experience with UPF for power intent specification.
- Track record of successfully bringing complex ASICs to market.
- Leadership experience or demonstrated ability to technically lead projects.