Key Responsibilities
- Develop and optimize RTL-to-GDS flow platforms for ASIC and SoC designs
- Collaborate with design teams to define and implement efficient design flows
- Automate and optimize physical design processes for performance and reliability
- Debug and resolve complex issues in RTL-to-GDS flow implementations
- Lead cross-functional teams to deliver robust design automation solutions
- Mentor junior engineers and drive best practices in design flow development
Requirements
- 7+ years of experience in RTL design, physical design, or EDA tool development
- Expertise in RTL-to-GDS flow platforms and ASIC design methodologies
- Strong proficiency in EDA tools and scripting languages (Tcl, Python)
- Experience with physical design, verification, and optimization
- Knowledge of ASIC flow automation and design for manufacturability